1. Field of the Invention
This invention relates to clock-tree structures and methods for synthesizing the clock-tree structure, and, more particularly, to a symmetrical clock-tree structure that has a minimized clock skew and enhanced process-variation tolerance, and a method for synthesizing the clock-tree structure.
2. Description of Related Art
With the rapid growth of complexity in current chip design, modern circuit systems mainly employ a synchronization system design. In the synchronization system, element blocks or subsystems in an integrated circuit or a printed circuit board have to operate at a consistent clock to meet the synchronous requirement. In practice, a clock source is installed to be in charge of generating a clock signal commonly used by the blocks or subsystems. However, since distances from the clock source to the blocks or subsystems differ from one another, the clock used by blocks or subsystems suffers some errors, which are called clock skew.
In a high-speed chip synchronous system, a clock tree that has less clock skew may effectively improve the clock speed. With the progress of manufacturing processes, process variation may affect the clock tree significantly, which causes the optimization of clock skew more difficult. According to the prior art, the majority of clock tree synthesizing techniques rely on timing models to estimate clock skew. The accuracy and complexity of the timing model dominates the quality and efficiency of the clock tree synthesis techniques. In general, a model having a higher accuracy may obtain less clock skew, in the cost of longer synthesizing time. Furthermore, modern timing models are not qualified to address the high accuracy required in high-speed chips. Inevitably, simulation techniques thus come to the market to estimate clock skew. However, the simulation techniques may cause a clock tree to take up to a couple of hours to be synthesized completely, which severely affects the convergence time of a whole chip design flow.
A dilemma of getting high accuracy or obtaining high efficiency always exists in synthesizing a clock tree. In particular, if process variation is further taken into consideration, it is even more difficult to optimize a clock-tree structure. The simulation techniques, though obtaining accurate timing information, may unnecessarily extend the synthesizing time. On the contrary, a compact timing model may speed up synthesizing, but cause the synthesized clock to suffer severe clock skew.
Therefore, how to provide a clock-tree structure and a method for synthesizing the clock-tree structure to solve the problems of the prior art is becoming one of the most urgent issues in the art.